ASICs

ASICs

Realized ASIC projects.
The research activities of the ASIC group focus mainly on the development of multichannel readout ASICs for neurobiology, X-ray imaging and high energy physics applications and in the last two years also in RF designs. Below is the list of projects realized by the members of ASICS group.
 

Fabricated ASICS

ChaSE Jr ChaSE Jr

Technology:   CMOS 40 nm
Area:   2.0 mm x 4.5 mm
Year(s):   2016
Place:   DME, AGH UST, Cracow
Description:   Prototype high speed pixel chip for semiconductor detector readout.
STS/MUCH-XYTER2 STS/MUCH-XYTER2

Technology:   UMC 180 nm CMOS MM/RF
Area:   10 x 6.75 mm2
Year(s):   2016
Place:   DME, AGH UST, Cracow
Description:   A prototype 128-channel charge and amplitude measurement ASIC for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter (CBM) experiment at FAIR, Germany.
DSToTIC2 DSToTIC2

Technology:   CMOS UMC 180 nm
Area:   1.5 x 1.5 mm2
Year(s):   2014
Place:   DME, AGH UST, Cracow
Description:   8-channel dual-stage processing stage for silicon strip detectors with two-stage reset and on-chip reference DACs
N100 N100

Technology:   CMOS UMC 180 nm
Area:   5 x 5 mm2
Year(s):   2014
Place:   DME, AGH UST, Cracow
Description:   100-channel chip for stimulation, recording and neural spike detection
UFCXv2 UFCXv2

Technology:   CMOS TSMC 130 nm
Area:   10 x 20 mm2
Year(s):   2014
Place:   DME, AGH UST, Cracow
Description:   Final chip
PIX40v2 PIX40v2

Technology:   CMOS TSMC 40 nm
Area:   2.5 x 4 mm2
Year(s):   2014
Place:   DME, AGH UST, Cracow
Description:   Pixel matrix for X-ray detection with corrected C8P1 algorithm and low noise performance
UFCXv1 UFCXv1

Technology:   CMOS TSMC 130 nm
Area:   10 x 15 mm2
Year(s):   2013
Place:   DME, AGH UST, Cracow
Description:   Pixel prototype chip (NCRD project)
Pixel prototype 40 nm Pixel prototype 40 nm

Technology:   CMOS TSMC 40 nm
Area:   2.5 x 4 mm2
Year(s):   2013
Place:   DME, AGH UST, Cracow
Description:   Pixel matrix for X-ray detection, C8P1 algorithm, Flash ADC
NSoCMZ1 NSoCMZ1

Technology:   CMOS UMC 0.18 μm
Area:   5.0 x 5.0 mm2
Year(s):   2013
Place:   DME, AGH UST, Cracow
Description:   System On Chip for multichannel wireless neural signal recording
DSToTIC DSToTIC

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2013
Place:   DME, AGH UST, Cracow
Description:   8-channel prototype dual stage processing stage for silicon strip detectors
ARF_ADC ARF_ADC

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2013
Place:   DME, AGH UST, Cracow
Description:   4-bit flash ADC for pixel systems, 6-bit flash ADC with comparator redundancy
AFE8 AFE8

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2013
Place:   DME, AGH UST, Cracow
Description:   8 channel analog front-end readout chip dedicated for double-sided silicon microstrip sensors
NRSD8 NRSD8

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2013
Place:   DME, AGH UST, Cracow
Description:   8-channel chip for recording and neural spike detection
STSXYTER STSXYTER

Technology:   CMOS UMC 0.18 μm
Area:   10 x 6.5 mm2
Year(s):   2012
Place:   DMI, AGH UST Cracow, ZITI Heidelberg
Description:   128-channel time and amplitude digitalization chip for SSD with CBMnet interface
NeuroRf2 NeuroRf2

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2012
Place:   DMI, AGH UST, Cracow
Description:   2 versions of Rf transmiter and adc converter for SoC for multichannel neural signal activity monitoring
NeuAng01 NeuAng01

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2012
Place:   DMI, AGH UST, Cracow
Description:   8 signal conditioning channels for SoC for multichannel neural signal activity monitoring
NeuDig02 NeuDig02

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2012
Place:   DMI, AGH UST, Cracow
Description:   4 versions of rectifiers, LDO, bandgap, RAM memory & 4GHz RF transmiter for SoC for multichannel neural signal activity monitoring
Publications:   [128]
NrsRf NrsRf

Technology:   CMOS UMC 0.18 μm
Area:   5 x 5 mm2
Year(s):   2011
Place:   DMI, AGH UST, Cracow
Description:   64 channel wireless SoC for multichannel neural signal activity monitoring with stimulation and artifact reductions circuits
NeuDig01 NeuDig01

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2011
Place:   DMI, AGH UST, Cracow
Description:   controll circuit and adc converter for SoC for multichannel neural signal activity monitoring
Publications:   [163]
NR8 NR8

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2011
Place:   DMI, AGH UST, Cracow
Description:   8-channel chip for recording biomedical signals
Publications:   [83]
FSDR16 FSDR16

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2011
Place:   DMI, AGH UST, Cracow
Description:   16-channel front-end with 5th order complex shaping amplifier
Publications:   [153] [156]
NRS64 NRS64

Technology:   CMOS UMC 0.18 μm
Area:   5 x 5 mm2
Year(s):   2010
Place:   DMI, AGH UST, Cracow
Description:   64 signal conditioning channels for multichannel neural signal activity monitoring with stimulation and artifact reductions circuits
Publications:   [151] [142] [166]
VIPIC - in collaboration with Fermilab VIPIC – in collaboration with Fermilab

Technology:   3D Tezzaron, CMOS CHRT 0.35 μm
Area:   5.5 x 6,3 mm2 x 2
Year(s):   2010 – in production
Place:   DMI, AGH UST, Cracow and FermiLab USA
Description:   3D ASIC -Vertically Integrated Pixel Imaging Chip
Publications:   [186]
TOT_02 TOT_02

Technology:   CMOS UMC 0.18 μm
Area:   3 x 4,35 mm2
Year(s):   2010 – in production
Place:   DMI, AGH UST, Cracow
Description:   16-channel front-end with ToT & digital part for SSD
Publications:   [161]
SXD2 SXD2

Technology:   CMOS austriamicrosystem 0.35 μm
Area:   3 x 4,35 mm2
Year(s):   2010
Place:   DMI, AGH UST, Cracow
Description:   32-channel photon counting chip for CdTe detector
RF2 RF2

Technology:   CMOS UMC 0.18 μm
Area:   0,75 x 1,5 mm2
Year(s):   2010
Place:   DMI, AGH UST, Cracow
Description:   prototype low-power RF transmitter
ADC_10B ADC_10B

Technology:   CMOS UMC 0.18 μm
Area:   0,75 x 1,5 mm2
Year(s):   2010
Place:   DMI, AGH UST, Cracow
Description:   10-bit ADC
Publications:   [150] [152]
FPDR90 FPDR90

Technology:   CMOS TSMC 90nm
Area:   4 x 4 mm2
Year(s):   2010
Place:   DMI, AGH UST, Cracow
Description:   Prototype of fast readout for silicon pixel detector, matrix 40 x 32 pixel of 100 x 100 μm2 pixel size
Publications:   [139] [187] [189]
NRTs NRTs

Technology:   CMOS UMC 0.18 μm
Area:   1.5 x 1.5 mm2
Year(s):   2009
Place:   DMI, AGH UST, Cracow
Description:   4 versions of Rf transmiter for SoC for multichannel neural signal activity monitoring
RF_MZ RF_MZ

Technology:   CMOS UMC 0.18 μm
Area:   1,5 x 1,5 mm2
Year(s):   2009
Place:   DMI, AGH UST, Cracow
Description:   2 prototype low-power RF transmitters
TOT_01 TOT_01

Technology:   CMOS UMC 0.18 μm
Area:   3 x 1,5 mm2
Year(s):   2009
Place:   DMI, AGH UST, Cracow
Description:   31-channel front-end with ToT for SSD
Publications:   [140] [198]
PX90 PX90

Technology:   CMOS TSMC 90nm
Area:   4 x 4 mm2
Year(s):   2009
Place:   DMI, AGH UST, Cracow
Description:   First prototype of readout for silicon pixel detector, matrix 40 x 32 pixel of 100 x 100 μm2 pixel size
Publications:   [179] [182] [204]
SXD64 SXD64

Technology:   CMOS austriamicrosystem 0.35 μm
Area:   4.8 x 5 mm2
Year(s):   2009
Place:   DMI, AGH UST, Cracow
Description:   64-channel photon counting chip for CdTe detector
Publications:   [159] [162] [200] [205]
NEURO_B NEURO_B

Technology:   CMOS UMC 0.18 μm
Area:   2.5 x 5 mm2
Year(s):   2008
Place:   DMI, AGH UST, Cracow
Description:   64-channel readout ASIC for neurobiology experiments, architecture B
Publications:   [180] [185] [199] [202]
NEURO_A NEURO_A

Technology:   CMOS UMC 0.18 μm
Area:   2.5 x 5 mm2
Year(s):   2008
Place:   DMI, AGH UST, Cracow
Description:   64-channel readout ASIC for neurobiology experiments, architecture A
Publications:   [143] [180] [183] [185] [199] [202]
RG64 RG64

Technology:   CMOS austriamicrosystem 0.35 μm
Area:   3.9 x 5 mm2
Year(s):   2007
Place:   DMI, AGH UST, Cracow
Description:   64-channel fast single photon counting chip for Si strip detector
Publications:   [194] [195] [220]
FX24 FX24

Technology:   CMOS austriamicrosystem 0.35 μm
Area:   3.6 x 2.5 mm2
Year(s):   2005-2006
Place:   DNE, AGH UST, Cracow
Description:   24- channels of fast frond-end electronics with new PZC circuit, fast shaper and two discriminators per channel, internal correction circuit. Control logic, counters, RAM, LVDS, testing circuits.
Publications:   [209]
DEDIX DEDIX

Technology:   CMOS austriamicrosystem 0.35 μm
Area:   3.9 x 5 mm2
Year(s):   2005-2006
Place:   DNE, AGH UST, Cracow
Description:   64- channels of fast frond-end electronics with PZC circuit, shaper, two discriminators per channel, internal correction circuit. Control logic, counters, RAM, LVDS, testing circuits.
Publications:   [229] [255] [258] [262]
NEUROPLAT NEUROPLAT

Technology:   CMOS Alcatel-Mietec 0.5 μm
Area:   2.9 x 6.5 mm2
Year(s):   2003-2004
Place:   DNE, AGH UST, Cracow
Description:   64-channels with AC-coupling at the input, low noise preamplifier, new concept of pass-band filters, analog multiplexer, control block, shift registers and LVDS, DACs
Publications:   [257] [286] [289]
DTMROC DTMROC

Technology:   CMOS 0.25 μm
Area:   26 mm2
Year(s):   2000-2003
Place:   ATLAS Collaboration, CERN, Geneve
Description:   16-channel ASIC for TRT detector, each channel includes: TDC with 3ns resolution, digital memory, command decoder, DACs, temperature sensor
Publications:   [230] [283] [320] [327]
RX64DTHv1 and RX64DTHv2 RX64DTHv1 and RX64DTHv2

Technology:   CMOS austriamicrosystem 0.8 μm
Area:   3.7 x 6.5 mm2
Year(s):   2000-2002
Place:   DNE, AGH UST, Cracow
Description:   64-channel of low noise charge sensitive amplifier with shaper and two discriminators per channel. Pseudo-random counters, control logic, DACs, internal testing circuits.
Publications:   [267] [268] [276] [287] [290] [291] [292] [294]
BUSTUS BUSTUS

Technology:   CMOS Alcatec-Mietec 0.7 μm
Area:   3.8 x 1.6 mm2
Year(s):   2001-2002
Place:   DNE, AGH UST, Cracow
Description:   Testing chip with low noise amplifiers with new concept of the filters
Publications:   [279] [307] [319]
ABCD (several versions) ABCD (several versions)

Technology:   BiCMOS 0.8 μm
Area:   51 mm2
Year(s):   1998-2002
Place:   ATLAS Collaboration, CERN, Geneve
Description:   128-channels readout for SSD working in SCT ATLAS detector
Publications:   [254] [264] [265] [265] [269] [282] [347] [347] [348] [354]
NEURO64 (Neurochip) NEURO64 (Neurochip)

Technology:   CMOS Alcatel-Mietec 0.7 μm
Area:   4 x 6.5 mm2
Year(s):   1999-2001
Place:   DNE, AGH UST, Cracow
Description:   64-channels of low noise preamplifier with very low frequency AC coupling circuits, pass-band filters, analog multiplexer, control block, shift registers and LVDS
Publications:   [266] [280] [293] [296] [308] [310] [311] [312] [325]
RX64 RX64

Technology:   CMOS austriamicrosystem 0.8 μm
Area:   3.7 x 6.5 mm2
Year(s):   1999-2000
Place:   DNE, AGH UST, Cracow
Description:   64-channel of low noise charge sensitive amplifier with shaper and discriminator. Pseudo-random counters, control logic, DACs
Publications:   [275] [284] [285] [288] [297] [298] [299] [300] [301] [304] [306] [309] [314] [315] [316] [318] [321] [322] [328] [330] [338]
XCOUNT32 XCOUNT32

Technology:   CMOS austriamicrosystem 1.2 μm
Area:   1.7 x 3.3 mm2
Year(s):   1997-1999
Place:   DNE, AGH UST, Cracow
Description:   32-channels of counters and RAMs with control logic
Publications:   [332]
SCTA (several versions) SCTA (several versions)

Technology:   BiCMOS 0.8 μm
Area:   9.3 x 6.9 mm2
Year(s):   1998-1999
Place:   ATLAS Collaboration, CERN, Geneve
Description:   128-channel analogue readout for SSD, 40-MHz analogue RAM + multiplexer, control block
Publications:   [302] [331] [335] [340] [355] [362]
RX32 and RX32N RX32 and RX32N

Technology:   CMOS austriamicrosystem 0.8 μm
Area:   1.8 x 3.3 mm2
Year(s):   1997-1999
Place:   DNE, AGH UST, Cracow
Description:   32-channel of low noise charge sensitive amplifier with shaper and discriminator
Publications:   [326] [332] [333] [336] [339] [346]
NEURO32 NEURO32

Technology:   CMOS Mietec 0.7 μm
Area:   4.3 x 4.0 mm2
Year(s):   1999
Place:   DNE, AGH UST, Cracow
Description:   32-channels of low noise preamplifier with very low frequency AC coupling circuits, pass-band filters, analog multiplexer and analog multiplexer
Publications:   [278] [296] [329] [337]
NEUROCHIP NEUROCHIP

Technology:   CMOS Mietec 2.0 μm
Area:   2.2 x 4.2 mm2
Year(s):   1997-1998
Place:   DNE, AGH UST, Cracow
Description:   testing chip with low noise preamplifier and low frequency filters
Publications:   [353]
SCTB SCTB

Technology:   BiCMOS 0.8 μm
Area:   6.1 x 5.2 mm2
Year(s):   1996-1997
Place:   ATLAS Collaboration, CERN, Geneve
Description:   128-channel fast binary readout for SSD, digital memmory, mix-mode design
Publications:   [334] [343] [350] [362]
NEURO-1 NEURO-1

Technology:   CMOS Mietec 0.7 μm
Area:   3 x 2 mm2
Year(s):   1998
Place:   DNE, AGH UST, Cracow
Description:   Multichannel ASIC for neurobiology experiments
Publications:   [345]
XRAY16 XRAY16

Technology:   CMOS austriamicrosystem 1.8 μm
Area:   2.8 x 2 mm2
Year(s):   1996-97
Place:   DNE, AGH UST, Cracow
Description:   16-channel amplifier-shaper-comparator chip
Publications:   [356]
APC16 APC16

Technology:   CMOS austriamicrosystem 1.2 μm
Area:   2.8 x 2 mm2
Year(s):   1995-1996
Place:   DNE, AGH UST, Cracow
Description:   16-channel amplifier-comparator chip
Publications:   [245] [361]